The present disclosure relates generally to semiconductor devices and, more particularly, to a spacer element associated with a semiconductor device.
Conventional semiconductor device fabrication processes, such as used in the fabrication of MOSFET devices, utilize a technique of forming spacer elements (spacers). In MOSFET fabrication, spacers assist in the control and definition of the implantation of dopants in the source and drain regions of a device. In particular, spacers may be used to control and define a lightly-doped drain (LDD) region of a device. The LDD region allows for a more gradual transition from a drain and/or source region to the gate region and is therefore advantageous in that it reduces the electric field created and thereby mitigates short channel effects, reduces hot carrier generation, and increases junction breakdown voltage. To perform these functions, a spacer is typically formed coupled to, and/or abutting, the gate of a device. A spacer may also be useful in passivating a surface to which it is coupled, such as a gate electrode sidewall.
In a conventional process, a plurality of gates are often formed in close proximity on a substrate. The gates are formed such that there is a gap (space) between each gate. Each gate, and associated electrical contacts, require isolation from adjacent gate and/or contact structures in order to prevent, for example, contact-to-contact leakage. This isolation may be provided by an isolating layer (such as, an interlayer dielectric (ILD) layer), formed on the substrate. The isolating layer may fill the gap between the gates and/or surround the gate and contacts.
The typical conventional spacer is a D-shaped spacer, or a spacer having a geometry of a D-shape (rounded). D-shaped spacers, as well as other conventional spacer geometries, are disadvantageous in that they can cause voids in layers subsequently deposited over the spacers and gate elements, such as the isolating layer described above. As dimensions shrink with increasing technology demands, devices become more closely arranged on a semiconductor substrate. Consequently, the distance between the gates, the size of the gap between gates, shrinks. A smaller gap is more difficult to fill with subsequent layers of material, such as material that can isolate one device from another. The geometry of conventional spacers, such as the D-shaped spacers, provides a difficult reentrant profile (angle of entry) for the gap between the gates. This difficulty may cause the subsequent layers filling the gap to have voids in the region of the gap. These voids, if present in a layer such as a dielectric layer, may cause contact-to-contact leakage. These issues can be exacerbated as shallow trench isolation (STI) oxide loss becomes typical in the state of the art fabrication as recesses are formed in the STI oxide region due to the semiconductor processes after the STI formation. The STI loss regions may be difficult to fill using conventional geometry spacers. Thus, a spacer geometry that allows subsequent layers to more adequately fill the gap between gates is desired, for example, to reduce potential leakage.
Furthermore, conventional geometry spacers, such as D-shaped spacers, may cause cracks in layers formed on the spacers. For example, D-shaped spacers provide a high stress on subsequent layers. As technology progresses, the subsequent layers are required to be thinner, further exacerbating the stress on the layer. Thus, a spacer geometry that allows subsequent layers to have a lower stress environment is desired.
As such, an improved spacer geometry is desired.